Aegis – open-source FPGA silicon (github.com) AI

Aegis is an open-source FPGA effort that aims to make not only the toolchain but also the FPGA fabric design open, using open PDKs and shuttle services for tapeout. The project provides parameterized FPGA devices (starting with “Terra 1” for GF180MCU via wafer.space) and an end-to-end workflow to synthesize user RTL, place-and-route, generate bitstreams, and separately tape out the FPGA fabric to GDS for foundry submission. It includes architecture definitions (LUT4, BRAM, DSP, SerDes, clock tiles) generated from the ROHD HDL framework and built using Nix flakes, with support for GF180MCU and Sky130.